DDR3 Simulation and Validation

Client Project: DDR3 Simulation and Validation

Project Description

Client needed to verify Signal Integrity of DDR3 memory controller in a server application with support for multiple memory module configurations.

Tools & Equipment Used

Synopsys HSPICE was used for simulation exploration of system design variables. Internal impedance calculators was used to determine impedance based upon different stackup configurations and Synopsys 2.5 field solver was used to generate lossy W element transmission line models. Custom scripts was used for data post processing and waveform analysis.

Overview of Work Performed

A full system simulation plan was put into place to account for all system design variables and find the optimal performance for each memory configuration in the server. Initial simulations narrowed down overall solution space to define such variables as motherboard trace impedance. Memory controller IBIS models generated from SPICE models and PCB trace models generated in field solver based upon stackup of server PCB. The package layout including crosstalk was also considered in the overall analysis. Monte Carlo analysis was used along with a psuedo Design of Experiment for final validation of selected system design variables. Custom scripts were created to setup, simulate, analyze, and report final validation results for timing and noise margin analysis.

Final Results

Using a robust simulation plan allowed for easy selection of design variables that has biggest impact on available margin such as motherboard trace impedance. The combination of Monte Carlo analysis and psuedo Design of Experiment allowed for full validation of memory controller in a wide configuration of server memory settings. Validation data provided key design variables to allow for sucessful server memory configuration at targeted speed.

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