Design Rule Checker for Signal Integrity

IBIS DRC - Signal Integrity IBIS Simulator Design Rule Checker

IBIS DRC is a Design Rule Checker for Signal Integrity analysis that automatically runs over 75+ design rules to validate IBIS models. Go beyond the IBIS Parser to find errors that the IBIS Parser can't find. Verify output impedance, edge rates, overclocked buffers, and over 75+ custom design rule checks. Import your vendor IC datasheet for faster and more accurate model checking. With built-in simulation and correlation features IBIS DRC is a complete solution to validating your Signal Integrity designs.


Features include:

    Automatically run over 75+ design rule checks on IC vendor IBIS models
    Find and fix IBIS model issues and errors with easy to use GUI editor
    Simulate IBIS model into test loads with supported IBIS simulators
    Import model correlation data from IC vendor or lab measurement for complete solution
    Easily create HTML reports and build your own validated CAD model library for Signal Integrity
    Schematic simulation for topology and termination Signal Integrity analysis with suported IBIS simulators

Feature Tour - Automatic Quality Checks

IBIS DRC uses over 75+ built-in quality checks based off of the IBIS Specification and the IC vendor datasheet to provide a comprehensive quality report.

Feature Tour - Built-in IBIS Simulation and Correlation

Simulate and correlate IBIS models with supported IBIS Simulators for complete simulation to hardware correlation.


IBIS DRC is no longer being actively developed.