Full Chip Power Integrity Analysis

Client Project: Full Chip Power Integrity Analysis for SerDes

Project Description

Client needed to validate the power delivery network of a SerDes interface in a full system to make sure the jitter interface specification was not exceeded.

Tools & Equipment Used

Ansoft SiWave was used to model the current density of the combined die, package, and printed circuit board. Decap placement was considered for the package and PCB and the impedance of the entire network was plotted against different variables. S-parameter models and equivalent broadband models was extracted using SiWave and used in Synopsys HSPICE to simulate the impedance of the network in the frequency domain and the time domain.

Overview of Work Performed

A full 3D field solver was used to extract accurate models of the impedance network from the die through the package and out to the printed circuit boaard. The models were used in both frequency domain and time domain simulations to validate the impact the power delivery network had on the jitter of the high-speed SerDes. The frequency domain analysis allowed visualization and segmentation of the overall decap strategy. The time domain simulation showed the actual transient noise induced on the SerDes interface that was used to translate into induced jitter based upon the SerDes IO design.

Final Results

By utilizing both frequency domain and time domain analysis methods the induced jitter on the SerDes interface due to internal interface switching and other interace buses switching was determined to not exceed the overall interface jitter specification.

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