Projects

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DDR3 Simulation and Validation
Client: Semiconductor Company

I helped a client validate their DDR3 memory controller across a wide matrix of memory modules in a server configuration. Full system simulations for timing and noise margin were performed and optimizations through Monte Carlo analysis and psuedo Design of Experiment provided design guidelines to meet the target specifications.

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Full Chip Power Integrity Analysis
Client: Semiconductor Company

My client needed to understand the impact the power delivery network of their chip in a full system would have on the high-speed SerDes interface jitter specification. Using advanced 3D field solver tools the complete system impedance was analyzed and the analysis results allowed upfront design decisions on selecting the proper amount of on-die capacitance versus the inductance of the package and PCB.

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Research Paper on IBIS Simulation Model Quality
Client: Internal

As part of my continuing work in device modeling I undertook my own survey of the quality of IBIS models in the semiconductor industry. I reviewed and categorized a sample size of availble IBIS simulation models and also did an informal survey of IBIS model users to put together a complete picture of what's happening in the industry. Some of the results were surprising, others were disappointing, and overall a fascinating look at how device modeling for Signal Integrity is being handled today.

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