Flight Time Delay with IBIS Models

Flight Time Delay with IBIS Models

By Timothy Coyle

Using IBIS Models for Setup and Hold Time Analysis

One of the goals of simulating a system with an IBIS model is to validate the setup and hold time at the receiver in a given interface. The best way to understand how timing works with an IBIS model is to walk through an example. In the following example we will use a common clock design but the information will apply to a source synchronous design as well.

The above image shows a common clock architecture block diagram such as a PCI bus. A single clock is shared between the driver and receiver. Data is clocked out of the driver on one clock edge and received at the receiver on the next clock edge. In a common clock design you have one clock cycle to get the data from the driver to the receiver.

Time to Clock Out Delay Tco

The Time to Clock Out (usually abbreviated as Tco) is the delay from the input clock to the output data of the driver at a defined measurement point into a test load. A defined test load is used rather than the system load so the device timing can be defined independent of system variables such as jitter.

In IBIS this defined test load is the sub keywords Vref, Rref, Cref, and Vmeas under the [Model] keyword. The time it takes the IBIS output buffer to reach the voltage threshold level Vmeas is the Tco or sometimes called Time to Vmeas.

The simulated Tco of an IBIS output driver is not the same as the Tco defined in the device datasheet. This is because an IBIS model only contains the IV and VT data of an IO buffer and not all of the internal logic that actually makes up the real Tco value. So you cannot use an IBIS model for internal timing like the input to output propagation delay.

Flight Time Delay Tprop

The time it takes the signal to propagate from the driver to the receiver is called the flight time delay which we have defined as Tprop. The flight time delay is calculated as the delay at the receiver minus the Tco. But which Tco value do we use?

As you might have guessed we will simulate the IBIS driver into the test load to get the simulated IBIS Tco value and that will be used in the flight time delay calculation. This way the flight time delay accounts only for the delay of the interconnect and not any of the driver delay. This is why the IBIS Tco value does not need to be the same as the real device Tco since it is always subtracted out in the flight time delay calculation.

We really only care about the delay time of the interconnect path from the driver to the receiver in our simulation. This will account for all sorts of system variables that we put in like crosstalk, jitter, and so on. Than the real device Tco of the driver and setup and hold time requirement of the receiver are used with the simulated flight time to calculate the final setup and hold time.

Setup and Hold Time: Putting It All Together

Once we have the flight time delay we can calculate the final timing at the receiver for setup and hold time margin. We will show the setup time margin equation as an example.

For a setup time calculation, remember that we have one clock cycle to get the data from the driver to the receiver. So all of the delays are subtracted from the clock period and we need to end up with positive margin.

Tsetup_margin = Tcycle – Tco – Tflight – Tskew – Tjitter – Tsetup

In the above equation the Tcycle is the clock period, the Tco is the Time to Clock Out from the datasheet, the Tflight is the delay of the interconnect from simulation, the Tskew is the difference of the clock arriving at the driver and receiver, the Tjitter is the cycle-to-cycle variation of the clock, and the Tsetup is the required setup time at the receiver.

From the setup equation it can be seen why the flight time delay from the system level simulation using an IBIS model is critical. If the flight time delay is not properly calculated from the IBIS model simulations it will give the wrong results in the final setup and hold time calculations.

References and Links

Using IBIS models in system level simulations to obtain the flight time delay is pretty straight forward. However it can take some thought to understand and convince yourself that you can use the device datasheet Tco and the simulated flight time (with the simulated Tco subtracted out) to come up with correct setup and hold time margins. Below are some references to understanding the flight time calculation and timing equations better.

“Using IBIS Models for Timing Analysis”, TI Application Note # SPRA839A, 2007.

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