IBIS Model Overclocking Issue

Over Clocking VT Data

By Timothy Coyle

Why Over Clocking VT Data is Bad

SThe VT time window length of a VT data table needs to be long enough for the signal to reach steady state but it cannot be too long. The VT data is used to turn the pullup and pulldown IV curves on and off so it essentially defines the actual switching frequency of the IBIS model in a simulator.

Determining the Switching Frequency Based Upon the IBIS Data

The image above shows the concept of over clocking. The total VT time window of a data table should be less than ½ the data period in order to avoid over clocking. The time window should be shorter than the pulse width of the highest frequency on the interface. Simulation tools will switch the IBIS data based upon the input data frequency but if the input frequency is faster than the actual IBIS VT data the simulator will try to switch the IBIS output before the VT table data transition has occurred.

As an example, consider a 100 Mhz signal that has a 10 nsec period and pulse width of 5 nsec. The total VT time window length should be less than 5 nsec.

It should also be noted that most modern simulators look for this issue now and most often can still simulate with the IBIS data (even if over clocked) but either an error will occur or more likely the simulator will shorten the VT time window length but that can cause accuracy issues that are difficult to trace.

Dead Time and Lead-In Time

In a VT data curve you really only care about the portion of the signal from right before it starts to transition to right after it completes the transition and reaches steady state. Any time before that (sometimes called the lead-in time) and any time after that (sometimes called the dead time) is extra data that is not useful. The terms ‘lead-in time’ and ‘dead time’ are often used interchangeably whether there is extra time in the beginning or end of a signal transition.

For example, let’s say you run a SPICE simulation to generate a rising VT waveform. Due to uncontrollable circuit behavior it takes 10 nsec for the signal to start to transition and reaches steady state in an additional 5 nsec. You can shift your VT waveform along the time axis to get rid of that excessive lead-in time or dead time. The same idea applies to data after the signal has reached steady state.

The above image shows the VT data of an output buffer for the MIN and MAX process corners. It also shows the appropriate time window length. Sometimes due to excessive lead in time a signal transition will occur after the required VT time length window. By trimming the lead in time you can still meet your VT time window length requirement to avoid an over clocking situation. As you can see you can trim the VT data curves independent of the process corner but you have to maintain the same timing relationship in each rising and falling VT waveform pair set. So if you trim 5 nsec form the MIN process corner of a rising VT waveform you should do the same for the MIN process corner of the corresponding falling VT waveform.

References and Links

“Solving Over Clocking Issues with IBIS Models”, Haller, XrossTalk Magazine, June 2008.

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