Publications

Optimize Signal Integrity Simulations

Simulate Twice, Design Once

By Timothy Coyle

Some Useful Advice on How to Optimize Your Simulations

The advances in EDA (electronic design automation) simulation software has made it extremely easy to quickly setup and run a simulation. In a matter of a few minutes you can be looking at waveforms and reams of data about your design. It should be easy enough to pick out your design parameters and call it a day, right? Hold on cowboy, because there’s a little more to it than that. Like anything in life if you do a little preparation up front and some planning you can actually cut your simulation time in half and get the answers to the questions you really need rather than a bunch of random simulation data. Read on for a few simulation tips to make you a rock star.

Simulate Once: Pre-layout

Why wait until your circuit or printed circuit board design is done to start simulating? Pre-layout simulation can be a valuable tool to narrow in on what design parameters really matter and which one’s don’t. Let’s take another look at a DDR2 memory interface. What drive strength settings should you design in to support the many different module settings and loading? You can assume 50 Ohms will work best and base all of your work on it only to find out that for a half of your intended use cases a 40 Ohm drive strength would have worked better.

The best way to optimize pre-layout simulation is to have on-going simulations from the time the product is being architected all the way through initial placement and route studies. This allows you to make data based decisions on a huge number of design decisions like topology, IO buffer characteristics, pick termination values, validate setup/hold timing, and more.

Simulate Twice: Post-layout

Now that you have spent your valuable time up front in your project you already have your solution space design metrics. You know what termination values will work best, the most robust topology, and a whole list of metrics to pick data from. Now all you have to do is validate what was actually done and this is what we call the post-layout stage. The number of simulations you run in this stage should be significantly smaller than the pre-layout stage. Remember, you are just validating your pre-layout assumptions. But you are also making sure that any changes that were made (and there are always changes) didn’t break your design. Let’s say your pre-layout analysis showed that 35 Ohm trace impedance would give you the best design margins but it would be too expensive to manufacture a tolerance like that so you went with 40 Ohms. You want to know that you still have margin, right? This way you can compare the results of the actual design layout against your pre-layout assumptions. It’s best to use critical nets/paths for this stage to make sure you still have margin before you spend lots of dough on full manufacturing runs.

Garbage In = Garbage Out

And that brings us to our next tip: garbage in equal’s garbage out. All of your simulation assumptions will directly impact your results. So you need to be disciplined and quality check all of your simulation models and setup methodologies. There are lots of ways to do this but in general you want to quality check simulation models from suppliers and verify your simulation tool flow is giving you the expected results. You may find out that while your PCB trace models seem accurate your board house is giving you something more than 10% tolerance you accounted for. So you can work with your board house (and other suppliers) to correlate your model data.

Of course the best way to do this is to use a real design and correlate your simulation results with actual lab measured data for specific use cases. This should be done with each new generation of device technology. This will provide a solid baseline for making sure what you see in simulation is “real” and not a figment of some haphazard programmer that you are now at the mercy of. Take it from me: if you skip this important step you mine as well put an error percentage range of +/-20% on all of your simulation results.

Constraint Managers Can Be Your Friend

Many PCB designers do not like Constraint Managers that are built into PCB layout tools. They can slow the tool down significantly and waste your time with an endless supply of useless error and warning messages. But if you push through that and find a flow to use the core features of a constraint manager you will save your company both time and money. The key to optimizing a constraint manager is figuring out what you need to turn on and off in the tool to make it useful. Think about the old days of using just a checklist filled out by the system designer or architect: route these signals like this, keep this trace below this length, and so on. Then we went to a spreadsheet and now it’s all interactive and cloud computing. Unfortunately it’s mostly trial and error but when you do find a flow that works the constraint manager is invaluable in keeping the final layout design within spec. This preserves all of the upfront work that was done in the pre-layout simulation stage and solves the usual suspect communication issues that always come up as in “oh, you didn’t want your clock signal routed right next to your noisy TTL signals?” Take the time to learn a constraint manager system (whether within your tool or independently) and you will notice that your design cycles and number of respins will go down.

Set Some Goals

Finally it should be mentioned that the whole point of simulation and validation is to prove that some design goal has been met. Too many engineers jump into simulating and layout guidelines without having clear goals in mind. Why do a lot of work if at the end of the day you don’t care about this signal or that connector? Choose your goals wisely and focus on those while ignoring the rest. Contrary to popular belief you can’t simulate everything at once accurately. Know thy goals should be your mantra.




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