Overview of IBIS Model

Overview of an IBIS Model

By Timothy Coyle

Getting to Know IBIS

The data in an IBIS model is made up of three main parts: the IV tables, the VT tables, and the various keyword values representing different parameters. Again you will see different terminology for the IBIS data such as IV tables, IV data, IV curves but it is all referencing the same current-voltage datasets.

The above image is a block diagram of a standard CMOS output buffer model in IBIS form. There is the traditional totem pole pmos/nmos architecture with an associated buffer capacitance. There can also be an ESD or clamping structure as well. Finally there are the package pin parasitic and some control input if present. The IV and VT data curves are used to represent the IO buffer (the CMOS driver and clamps) while the buffer capacitance is represented by a lumped capacitor value.

The IV Curves

The above image shows the IV curves for a standard CMOS driver. I like to describe the transistors as variable resistors and to generate the IBIS data you perform a DC voltage sweep to generate the current-voltage table. We’ll discuss the IV curve generation more in depth in later articles.

The above image shows the ground and power clamp IV curves. (The ESD diodes in the IBIS block diagram) The ESD structure can be found in output buffers (think tri-state buffers) as well as input buffers. IBIS models all ESD diode structures the same as “clamp” IV curves. The idea is very simple when you consider a diode: below ground and above Vcc the diodes will turn on and current will flow in order to protect the circuit. In reality most ESD structures are more complicated than a simple diode but this model holds up well to represent the circuit clamping affects.

The VT Curves

The above image shows the VT curves for a standard CMOS driver. While the IV curves can be used alone to represent the IO buffer with the addition of the VT curves the accuracy is increased dramatically because now there is information on when to turn the transistors on and off when switching states from low-to-high and high-to-low. I like to describe the VT curves as switches that work with the IV curves (variable resistors) to turn them on and off.

The IBIS Algorithm

The above image is a block diagram of a possible implementation of an IBIS algorithm to demonstrate how the IV and VT data can be used together to represent the IO buffer. The IV data is represented by voltage controlled resistors driven by voltage controlled current sources and those are turned on and off by the VT data curves. This is an oversimplification of how an IBIS algorithm could be implemented but it shows the relationship between the IV and VT data and why it is important.

References and Links

Some links on research discussing modeling IBIS data in simulation engines.

“Extraction of Transient Behavioral Model of Digital I/O Buffers From IBIS”, Tehrani, Chen, and Fang. Department of Electrical Engineering, State University of New York at Binghamton, 1996.

“The Development of Analog SPICE Behavioral Based on IBIS Model”, Wang, Tan. School of EEE, Nayang Technological University, 1999.

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